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| Ordering number : ENN6370A CMOS IC LC75808E, 75808W 1/8 to 1/10 Duty LCD Display Drivers with Key Input Function Overview The LC75808E and LC75808W are 1/8 to 1/10 duty LCD display drivers that can directly drive up to 600 segments and can control up to four general-purpose output ports. These products also incorporate a key scan circuit that accepts input from up to 30 keys to reduce printed circuit board wiring. Package Dimensions unit: mm 3151-QFP100E [LC75808E] 0.825 0.575 80 81 0.65 23.2 20.0 0.3 1.6 0.575 51 50 0.15 Features * Key input function for up to 30 keys (A key scan is performed only when a key is pressed.) * 1/8duty-1/4bias, 1/9duty-1/4bias, and 1/10duty-1/4bias drive schemes can be controlled from serial data. 1/8duty-1/4bias: up to 480 segments 1/9duty-1/4bias: up to 540 segments 1/10duty-1/4bias: up to 600 segments * Sleep mode and all segments off functions that are controlled from serial data. * Serial data I/O supports CCB format communication with the system controller. * Direct display of display data without the use of a decoder provides high generality. * Built-in display contrast adjustment circuit. * Up to 4 general-purpose output ports are included. * Independent LCD driver block power supply VLCD. * Provision of an on-chip voltage-detection type reset circuit prevents incorrect displays. * The INH pin is provided. This pin turns off the display, disables key scanning, and forces the general-purpose output ports to the low level. * RC oscillator circuit. 17.2 14.0 0.65 0.825 1.6 31 100 0.1 2.7 21.6 0.8 SANYO: QFP100E unit: mm 3181B-SQFP100 [LC75808W] 16.0 14.0 1.0 75 0.5 1.0 51 50 0.145 1.0 76 16.0 14.0 0.5 26 1.0 1 0.2 25 1.6max 100 1.4 0.1 0.5 0.5 SANYO: SQFP100 * CCB is a trademark of SANYO ELECTRIC CO., LTD. * CCB is SANYO's original bus format and all the bus addresses are controlled by SANYO. Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 31000RM (OT)/12800RM No. 6370 -1/39 0.8 1 30 3.0max 15.6 LC75808E, 75808W Pin Assignment No. 6370 -2/39 LC75808E, 75808W Specifications Absolute Maximum Ratings at Ta=25C, VSS=0V Parameter Maximum supply voltage Symbol VDD max VLCD max VIN1 Input voltage VIN2 VIN3 VOUT1 Output voltage VOUT2 VOUT3 IOUT1 Output current IOUT2 IOUT3 IOUT4 Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg VDD VLCD CE, CL, DI, INH OSC, KI1 to KI5, TEST VLCD1, VLCD2, VLCD3, VLCD4 DO OSC, KS1 to KS6, P1 to P4 VLCD0, S1 to S60, COM1 to COM10 S1 to S60 COM1 to COM10 KS1 to KS6 P1 to P4 Ta = 85C Conditions Ratings -0.3 to +7.0 -0.3 to +12.0 -0.3 to +7.0 -0.3 to VDD +0.3 -0.3 to VLCD +0.3 -0.3 to +7.0 -0.3 to VDD +0.3 -0.3 to VLCD +0.3 300 3 1 5 200 -40 to +85 -55 to +125 mW C C mA A V V Unit V Allowable Operating Ranges at Ta = -40 to +85C, VSS=0V Parameter Symbol VDD Supply voltage VDD VLCD, When the display contrast adjustment circuit is used VLCD, When the display contrast adjustment circuit is not used VLCD0 VLCD1 VLCD2 VLCD3 VLCD4 CE, CL, DI, INH KI1 to KI5 CE, CL, DI, INH, KI1 to KI5 OSC OSC OSC CL, DI CL, DI CE, CL CE, CL CE, CL CL CL :Figure 2 :Figure 2 :Figure 2 :Figure 2 :Figure 2 :Figure 2 :Figure 2 25 160 160 160 160 160 160 160 1.5 1.5 0 0.8 VDD 0.6 VDD 0 43 680 50 100 Conditions Ratings min 4.5 7.0 4.5 VLCD4 + 4.5 3/4 (VLCD0-VLCD4) 2/4 (VLCD0-VLCD4) 1/4 (VLCD0-VLCD4) typ max 6.0 11.0 V 11.0 VLCD VLCD0 VLCD0 VLCD0 1.5 6.0 VDD 0.2 VDD V V k pF kHz ns ns ns ns ns ns ns s s V V Unit VLCD Output voltage VLCD0 VLCD1 Input voltage VLCD2 VLCD3 VLCD4 Input high level voltage Input low level voltage Recommended external resistance Recommended external capacitance Guaranteed oscillation range Data setup time Data hold time CE wait time CE setup time CE hold time High level clock pulse width Low level clock pulse width DO output delay time DO rise time VIH1 VIH2 VIL ROSC COSC fOSC tds tdh tcp tcs tch toH toL tdc tdr DO, RPU = 4.7 k, CL = 10 pF *1 :Figure 2 DO, RPU = 4.7 k, CL = 10 pF *1 :Figure 2 Note: *1. Since DO is an open-drain output, these values depend on the resistance of the pull-up resistor RPU and the load capacitance CL. No. 6370 -3/39 LC75808E, 75808W Electrical Characteristics for the Allowable Operating Ranges Parameter Hysteresis Power-down detection voltage Input high level current Input low level current Input floating voltage Pull-down resistance Output off leakage current Symbol VH VDET IIH IIL VIF RPD IOFFH VOH1 Output high level voltage VOH2 VOH3 VOH4 VOL1 VOL2 Output low level voltage VOL3 VOL4 VOL5 VMID1 CE, CL, DI, INH: VI = 6.0 V CE, CL, DI, INH: VI = 0 V KI1 to KI5 KI1 to KI5: VDD = 5.0 V DO: VO = 6.0 V S1 to S60: IO = -20 A COM1 to COM10: IO = -100 A KS1 to KS6: IO = -500 A P1 to P4: IO = -1 mA S1 to S60: IO = 20 A COM1 to COM10: IO = 100 A KS1 to KS6: IO = 25 A P1 to P4: IO = 1 mA DO: IO = 1mA S1 to S60: IO = 20 A 2/4 (VLCD0 - VLCD4) -0.6 3/4 (VLCD0 - VLCD4) -0.6 1/4 (VLCD0 - VLCD4) -0.6 40 50 0.1 0.2 0.5 VLCD0 - 0.6 VLCD0 - 0.6 VDD - 1.0 VDD - 1.0 VLCD4 + 0.6 VLCD4 + 0.6 1.5 1.0 0.5 2/4 (VLCD0 - VLCD4) +0.6 3/4 (VLCD0 - VLCD4) +0.6 1/4 (VLCD0 - VLCD4) +0.6 60 100 250 500 5 kHz V V VDD - 0.5 VDD - 0.2 V 50 100 -5.0 0.05 VDD 250 6.0 Conditions CE, CL, DI, INH, KI1 to KI5 2.5 Ratings min typ 0.1 VDD 3.0 3.5 5.0 max Unit V V A A V k A Output middle level voltage *2 VMID2 COM1 to COM10: IO = 100 A VMID3 Oscillator frequency fosc IDD1 IDD2 ILCD1 COM1 to COM10: IO = 100 A OSC: ROSC = 43 k, COSC = 680 pF VDD :Sleep mode VDD: VDD = 6.0 V, outputs open,fosc = 50 kHz VLCD : Sleep mode VLCD : VLCD = 11.0 V Outputs open fosc = 50 kHz (When the display contrast adjustment circuit is used.) VLCD : VLCD = 11.0 V Outputs open fosc = 50 kHz (When the display contrast adjustment circuit is not used.) Current drain ILCD2 500 1000 A ILCD3 250 500 Note: *2. Excluding the bias voltage generation divider resistor built into VLCD0, VLCD1, VLCD2 , VLCD3, and VLCD4. (See Figure 1.) No. 6370 -4/39 LC75808E, 75808W To the common and segment drivers Excluding these resistors. Figure 1 1. When CL is stopped at the low level 2. When CL is stopped at the high level Figure 2 No. 6370 -5/39 LC75808E, 75808W Block Diagram No. 6370 -6/39 LC75808E, 75808W Pin Functions Pin S1 to S60 COM1 to COM10 Pin No. LC75808E 3 to 62 72 to 63 LC75808W 1 to 60 70 to 61 Segment driver outputs. Common driver outputs. Key scan outputs. Although normal key scan timing lines require diodes to be inserted in the timing lines to prevent shorts, since these outputs are unbalanced CMOS transistor outputs, these outputs will not be damaged by shorting when these outputs are used to form a key matrix. Key scan inputs. These pins have built-in pull-down resistors. General-purpose output ports. Oscillator connection. An oscillator circuit is formed by connecting an external resistor and capacitor at this pin. Serial data interface connections to the controller. Note that DO, being an open-drain output, requires a pull-up resistor. CE :Chip enable CL :Synchronization clock DI :Transfer data DO :Output data Function Active -- -- I/O q q Handling when unused OPEN OPEN KS1 to KS6 73 to 78 71 to 76 -- O OPEN KI1 to KI5 P1 to P4 79 to 83 84 to 87 77 to 81 82 to 85 H -- I q GND OPEN OSC 97 95 -- I/O VDD CE CL DI DO 100 1 2 99 98 99 100 97 H v -- -- I I I O OPEN GND INH 98 96 Input that turns the display off, disables key scanning, and forces the general-purpose output ports low. * When INH is low (VSS): * Display off S1 to S60 = "L" (VLCD4). COM1 to COM10 = "L" (VLCD4). * General-purpose output ports P1 to P4 = low (VSS) * Key scanning is disabled: KS1 to KS6 = low (VSS) * All the key data is reset to low. * When INH is high (VDD): * Display on * The states of the general-purpose output ports can be set by the PC1 to PC4 control data. * Key scanning is enabled. However, serial data can be transferred when the INH pin is low. This pin must be connected to ground. LCD drive 4/4 bias voltage (high level) supply pin. The level on this pin can be changed by the display contrast adjustment circuit. However, (VLCD0 - VLCD4) must be greater than or equal to 4.5 V. Also,external power must not be applied to this pin since the pin circuit includes the display contrast adjustment circuit. LCD drive 3/4 bias voltage (middle level) supply pin. This pin can be used to supply the 3/4 (VLCD0 - VLCD4) voltage level externally. LCD drive 2/4 bias voltage (middle level) supply pin. This pin can be used to supply the 2/4 (VLCD0 - VLCD4) voltage level externally. LCD drive 1/4 bias voltage (middle level) supply pin. This pin can be used to supply the 1/4 (VLCD0 - VLCD4) voltage level externally. LCD drive 0/4 bias voltage (low level) supply pin. Fine adjustment of the display contrast can be implemented by connecting an external variable resistor to this pin. However, (VLCD0 - VLCD4) must be greater than or equal to 4.5 V, and VLCD4 must be in the range 0 V to 1.5 V, inclusive. Logic block power supply connection. Provide a voltage of between 4.5 and 6.0V. LCD driver block power supply connection. Provide a voltage of between 7.0 and 11.0 V when the display contrast adjustment circuit is used and provide a voltage of between 4.5 and 11.0 V when the circuit is not used. Power supply connection. Connect to ground. L I VDD TEST 96 94 -- I -- VLCD0 90 88 -- 0 OPEN VLCD1 91 89 -- I OPEN VLCD2 92 90 -- I OPEN VLCD3 93 91 -- I OPEN VLCD4 94 92 -- I GND VDD 88 86 -- -- -- VLCD VSS 89 87 -- -- -- 95 93 -- -- -- No. 6370 -7/39 LC75808E, 75808W Serial Data Input 1. 1/8 duty x When CL is stopped at the low level. * When the display data is transferred. Display data Fixed data Display data Fixed data Display data Fixed data Display data Fixed data * When the control data is transferred. Control data Note: B0 to B3,A0 to A3 ........ CCB address DD ................................ Direction data No. 6370 -8/39 LC75808E, 75808W y When CL is stopped at the high level. * When the display data is transferred. Display data Fixed data Display data Fixed data Display data Fixed data Display data Fixed data * When the control data is transferred. Control data Note: B0 to B3,A0 to A3 ........ CCB address DD ................................ Direction data * CCB address: ....42H * D1 to D480: ........ Display data * KC1 to KC6: ........ Key scan output state setting data * PC1 to PC4: ........ General-purpose output port state setting data * CT0 to CT3, CTC: Display contrast setting data * SC: ...................... Segment on/off control data * SP: ...................... Normal mode/sleep mode control data * DT1, DT2: ............ Display technique setting data No. 6370 -9/39 LC75808E, 75808W 2. 1/9 duty x When CL is stopped at the low level. * When the display data is transferred. Display data Fixed data Display data Fixed data Display data Fixed data Display data Fixed data * When the control data is transferred. Control data Note: B0 to B3,A0 to A3 ........ CCB address DD ................................ Direction data No. 6370 -10/39 LC75808E, 75808W y When CL is stopped at the high level. * When the display data is transferred. Display data Fixed data Display data Fixed data Display data Fixed data Display data Fixed data * When the control data is transferred. Control data Note: B0 to B3,A0 to A3 ........ CCB address DD ................................ Direction data * CCB address: ...... 42H * D1 to D540: ........ Display data * KC1 to KC6: ........ Key scan output state setting data * PC1 to PC4: ........ General-purpose output port state setting data * CT0 to CT3, CTC: Display contrast setting data * SC: ...................... Segment on/off control data * SP: ...................... Normal mode/sleep mode control data * DT1, DT2: ............ Display technique setting data No. 6370 -11/39 LC75808E, 75808W 3. 1/10 duty x When CL is stopped at the low level. * When the display data is transferred. Display data Fixed data Display data Fixed data Display data Fixed data Display data Fixed data * When the control data is transferred. Control data Note: B0 to B3,A0 to A3 ........ CCB address DD ................................ Direction data No. 6370 -12/39 LC75808E, 75808W y When CL is stopped at the high level. * When the display data is transferred. Display data Fixed data Display data Fixed data Display data Fixed data Display data Fixed data * When the control data is transferred. Control data Note: B0 to B3,A0 to A3 ........ CCB address DD ................................ Direction data * CCB address: ...... 42H * D1 to D600: ........ Display data * KC1 to KC6: ........ Key scan output state setting data * PC1 to PC4: ........ General-purpose output port state setting data * CT0 to CT3, CTC: Display contrast setting data * SC: ...................... Segment on/off control data * SP: ...................... Normal mode/sleep mode control data * DT1, DT2: ............ Display technique setting data No. 6370 -13/39 LC75808E, 75808W Control Data Functions 1. KC1 to KC6: Key scan output state setting data These control data bits set the states of the key scan output pins KS1 to KS6. Output pin Key scan output state setting data KS1 KC1 KS2 KC2 KS3 KC3 KS4 KC4 KS5 KC5 KS6 KC6 For example, if KC1 to KC3 are set to 1, and KC4 to KC6 are set to 0, then the output pins KS1 to KS3 will output high levels (VDD) and the output pins KS4 to KS6 will output low levels (VSS) in the key scan standby state. Note that key scan output signal is not output from output pins that are set low. 2. PC1 to PC4: General-purpose output port state setting data These control data bits set the states of the general-purpose output ports P1 to P4. Output pin General-purpose output port state setting data P1 PC1 P2 PC2 P3 PC3 P4 PC4 For example, if PC1 and PC2 are set to 1, and PC3 and PC4 are set to 0, then the output pins P1 and P2 will output high levels (VDD) and the output pins P3 and P4 will output low levels (VSS). 3. CT0 to CT3, CTC: Display contrast setting data These control data bits set the display contrast. CT0 to CT3: Display contrast setting (11 steps) CT0 0 1 0 1 0 1 0 1 0 1 0 CT1 0 0 1 1 0 0 1 1 0 0 1 CT2 0 0 0 0 1 1 1 1 0 0 0 CT3 0 0 0 0 0 0 0 0 1 1 1 LCD drive 4/4 bias voltage supply VLCD0 level 0.94 VLCD = VLCD - (0.03 VLCD x 2) 0.91 VLCD = VLCD - (0.03 VLCD x 3) 0.88 VLCD = VLCD - (0.03 VLCD x 4) 0.85 VLCD = VLCD - (0.03 VLCD x 5) 0.82 VLCD = VLCD - (0.03 VLCD x 6) 0.79 VLCD = VLCD - (0.03 VLCD x 7) 0.76 VLCD = VLCD - (0.03 VLCD x 8) 0.73 VLCD = VLCD - (0.03 VLCD x 9) 0.70 VLCD = VLCD - (0.03 VLCD x 10) 0.67 VLCD = VLCD - (0.03 VLCD x 11) 0.64 VLCD = VLCD - (0.03 VLCD x 12) CTC: Display contrast adjustment circuit state setting CTC 0 1 Display contrast adjustment circuit state The display contrast adjustment circuit is disabled, and the VLCD0 pin level is forced to the VLCD level. The display contrast adjustment circuit operates, and the display contrast is adjusted. Note that although the display contrast can be adjusted by operating the built-in display contrast adjustment circuit, it is also possible to apply fine adjustments to the contrast by connecting an external variable resistor to the VLCD4 pin and modifying the VLCD4 pin voltage. However, the following conditions must be met: (VLCD0 - VLCD4) 4.5 V, and 1.5 V VLCD4 0 V. No. 6370 -14/39 LC75808E, 75808W 4. SC: Segment on/off control data This control data bit controls the on/off state of the segments. SC 0 1 Display state On Off However, note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting segment off waveforms from the segment output pins. 5. SP: Normal mode/sleep mode control data This control data bit controls the normal mode and sleep mode. SP 0 Normal mode Sleep mode 1 The common and segment pins go to the VLCD4 level and the oscillator on the OSC pin is stopped (although it operates during key scan operations) to reduce current drain. Note that the states of the general-purpose output ports P1 to P4 are set by PC1 to PC4 in the control data during sleep mode as well as normal mode. Mode 6. DT1, DT2: Display technique setting data These control data bits set the display technique. DT1 0 1 0 DT2 0 0 1 Display technique COM9 1/8 duty 1/4 bias drive 1/9 duty 1/4 bias drive 1/10 duty 1/4 bias drive Fixed at the VLCD4 level COM9 COM9 Output pins COM10 Fixed at the VLCD4 level Fixed at the VLCD4 level COM10 Note: COMn (n = 9 or 10): Common outputs No. 6370 -15/39 LC75808E, 75808W Display Data and Output Pin Correspondence 1. 1/8 duty Output Pin S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 COM1 D1 D9 D17 D25 D33 D41 D49 D57 D65 D73 D81 D89 D97 D105 D113 D121 D129 D137 D145 D153 D161 D169 D177 D185 D193 D201 D209 D217 D225 D233 D241 D249 D257 D265 D273 D281 D289 D297 D305 D313 D321 D329 D337 D345 D353 COM2 D2 D10 D18 D26 D34 D42 D50 D58 D66 D74 D82 D90 D98 D106 D114 D122 D130 D138 D146 D154 D162 D170 D178 D186 D194 D202 D210 D218 D226 D234 D242 D250 D258 D266 D274 D282 D290 D298 D306 D314 D322 D330 D338 D346 D354 COM3 D3 D11 D19 D27 D35 D43 D51 D59 D67 D75 D83 D91 D99 D107 D115 D123 D131 D139 D147 D155 D163 D171 D179 D187 D195 D203 D211 D219 D227 D235 D243 D251 D259 D267 D275 D283 D291 D299 D307 D315 D323 D331 D339 D347 D355 COM4 D4 D12 D20 D28 D36 D44 D52 D60 D68 D76 D84 D92 D100 D108 D116 D124 D132 D140 D148 D156 D164 D172 D180 D188 D196 D204 D212 D220 D228 D236 D244 D252 D260 D268 D276 D284 D292 D300 D308 D316 D324 D332 D340 D348 D356 COM5 D5 D13 D21 D29 D37 D45 D53 D61 D69 D77 D85 D93 D101 D109 D117 D125 D133 D141 D149 D157 D165 D173 D181 D189 D197 D205 D213 D221 D229 D237 D245 D253 D261 D269 D277 D285 D293 D301 D309 D317 D325 D333 D341 D349 D357 COM6 D6 D14 D22 D30 D38 D46 D54 D62 D70 D78 D86 D94 D102 D110 D118 D126 D134 D142 D150 D158 D166 D174 D182 D190 D198 D206 D214 D222 D230 D238 D246 D254 D262 D270 D278 D286 D294 D302 D310 D318 D326 D334 D342 D350 D358 COM7 D7 D15 D23 D31 D39 D47 D55 D63 D71 D79 D87 D95 D103 D111 D119 D127 D135 D143 D151 D159 D167 D175 D183 D191 D199 D207 D215 D223 D231 D239 D247 D255 D263 D271 D279 D287 D295 D303 D311 D319 D327 D335 D343 D351 D359 COM8 D8 D16 D24 D32 D40 D48 D56 D64 D72 D80 D88 D96 D104 D112 D120 D128 D136 D144 D152 D160 D168 D176 D184 D192 D200 D208 D216 D224 D232 D240 D248 D256 D264 D272 D280 D288 D296 D304 D312 D320 D328 D336 D344 D352 D360 Continued on next page. No. 6370 -16/39 LC75808E, 75808W Continued from preceding page. Output Pin S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 COM1 D361 D369 D377 D385 D393 D401 D409 D417 D425 D433 D441 D449 D457 D465 D473 COM2 D362 D370 D378 D386 D394 D402 D410 D418 D426 D434 D442 D450 D458 D466 D474 COM3 D363 D371 D379 D387 D395 D403 D411 D419 D427 D435 D443 D451 D459 D467 D475 COM4 D364 D372 D380 D388 D396 D404 D412 D420 D428 D436 D444 D452 D460 D468 D476 COM5 D365 D373 D381 D389 D397 D405 D413 D421 D429 D437 D445 D453 D461 D469 D477 COM6 D366 D374 D382 D390 D398 D406 D414 D422 D430 D438 D446 D454 D462 D470 D478 COM7 D367 D375 D383 D391 D399 D407 D415 D423 D431 D439 D447 D455 D463 D471 D479 COM8 D368 D376 D384 D392 D400 D408 D416 D424 D432 D440 D448 D456 D464 D472 D480 For example, the table below lists the segment output states for the S11 output pin. Display data D81 0 1 0 0 0 0 0 0 0 1 D82 0 0 1 0 0 0 0 0 0 1 D83 0 0 0 1 0 0 0 0 0 1 D84 0 0 0 0 1 0 0 0 0 1 D85 0 0 0 0 0 1 0 0 0 1 D86 0 0 0 0 0 0 1 0 0 1 D87 0 0 0 0 0 0 0 1 0 1 D88 0 0 0 0 0 0 0 0 1 1 The LCD segments for COM1 to COM8 are off. The LCD segment for COM1 is on. The LCD segment for COM2 is on. The LCD segment for COM3 is on. The LCD segment for COM4 is on. The LCD segment for COM5 is on. The LCD segment for COM6 is on. The LCD segment for COM7 is on. The LCD segment for COM8 is on. The LCD segments for COM1 to COM8 are on. Output pin state (S11) No. 6370 -17/39 LC75808E, 75808W 2. 1/9 duty Output Pin S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 COM1 D1 D10 D19 D28 D37 D46 D55 D64 D73 D82 D91 D100 D109 D118 D127 D136 D145 D154 D163 D172 D181 D190 D199 D208 D217 D226 D235 D244 D253 D262 D271 D280 D289 D298 D307 D316 D325 D334 D343 D352 D361 D370 D379 D388 D397 COM2 D2 D11 D20 D29 D38 D47 D56 D65 D74 D83 D92 D101 D110 D119 D128 D137 D146 D155 D164 D173 D182 D191 D200 D209 D218 D227 D236 D245 D254 D263 D272 D281 D290 D299 D308 D317 D326 D335 D344 D353 D362 D371 D380 D389 D398 COM3 D3 D12 D21 D30 D39 D48 D57 D66 D75 D84 D93 D102 D111 D120 D129 D138 D147 D156 D165 D174 D183 D192 D201 D210 D219 D228 D237 D246 D255 D264 D273 D282 D291 D300 D309 D318 D327 D336 D345 D354 D363 D372 D381 D390 D399 COM4 D4 D13 D22 D31 D40 D49 D58 D67 D76 D85 D94 D103 D112 D121 D130 D139 D148 D157 D166 D175 D184 D193 D202 D211 D220 D229 D238 D247 D256 D265 D274 D283 D292 D301 D310 D319 D328 D337 D346 D355 D364 D373 D382 D391 D400 COM5 D5 D14 D23 D32 D41 D50 D59 D68 D77 D86 D95 D104 D113 D122 D131 D140 D149 D158 D167 D176 D185 D194 D203 D212 D221 D230 D239 D248 D257 D266 D275 D284 D293 D302 D311 D320 D329 D338 D347 D356 D365 D374 D383 D392 D401 COM6 D6 D15 D24 D33 D42 D51 D60 D69 D78 D87 D96 D105 D114 D123 D132 D141 D150 D159 D168 D177 D186 D195 D204 D213 D222 D231 D240 D249 D258 D267 D276 D285 D294 D303 D312 D321 D330 D339 D348 D357 D366 D375 D384 D393 D402 COM7 D7 D16 D25 D34 D43 D52 D61 D70 D79 D88 D97 D106 D115 D124 D133 D142 D151 D160 D169 D178 D187 D196 D205 D214 D223 D232 D241 D250 D259 D268 D277 D286 D295 D304 D313 D322 D331 D340 D349 D358 D367 D376 D385 D394 D403 COM8 D8 D17 D26 D35 D44 D53 D62 D71 D80 D89 D98 D107 D116 D125 D134 D143 D152 D161 D170 D179 D188 D197 D206 D215 D224 D233 D242 D251 D260 D269 D278 D287 D296 D305 D314 D323 D332 D341 D350 D359 D368 D377 D386 D395 D404 COM9 D9 D18 D27 D36 D45 D54 D63 D72 D81 D90 D99 D108 D117 D126 D135 D144 D153 D162 D171 D180 D189 D198 D207 D216 D225 D234 D243 D252 D261 D270 D279 D288 D297 D306 D315 D324 D333 D342 D351 D360 D369 D378 D387 D396 D405 Continued on next page. No. 6370 -18/39 LC75808E, 75808W Continued from preceding page. Output Pin S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 COM1 D406 D415 D424 D433 D442 D451 D460 D469 D478 D487 D496 D505 D514 D523 D532 COM2 D407 D416 D425 D434 D443 D452 D461 D470 D479 D488 D497 D506 D515 D524 D533 COM3 D408 D417 D426 D435 D444 D453 D462 D471 D480 D489 D498 D507 D516 D525 D534 COM4 D409 D418 D427 D436 D445 D454 D463 D472 D481 D490 D499 D508 D517 D526 D535 COM5 D410 D419 D428 D437 D446 D455 D464 D473 D482 D491 D500 D509 D518 D527 D536 COM6 D411 D420 D429 D438 D447 D456 D465 D474 D483 D492 D501 D510 D519 D528 D537 COM7 D412 D421 D430 D439 D448 D457 D466 D475 D484 D493 D502 D511 D520 D529 D538 COM8 D413 D422 D431 D440 D449 D458 D467 D476 D485 D494 D503 D512 D521 D530 D539 COM9 D414 D423 D432 D441 D450 D459 D468 D477 D486 D495 D504 D513 D522 D531 D540 For example, the table below lists the segment output states for the S11 output pin. Display data D91 0 1 0 0 0 0 0 0 0 0 1 D92 0 0 1 0 0 0 0 0 0 0 1 D93 0 0 0 1 0 0 0 0 0 0 1 D94 0 0 0 0 1 0 0 0 0 0 1 D95 0 0 0 0 0 1 0 0 0 0 1 D96 0 0 0 0 0 0 1 0 0 0 1 D97 0 0 0 0 0 0 0 1 0 0 1 D98 0 0 0 0 0 0 0 0 1 0 1 D99 0 0 0 0 0 0 0 0 0 1 1 The LCD segments for COM1 to COM9 are off. The LCD segment for COM1 is on. The LCD segment for COM2 is on. The LCD segment for COM3 is on. The LCD segment for COM4 is on. The LCD segment for COM5 is on. The LCD segment for COM6 is on. The LCD segment for COM7 is on. The LCD segment for COM8 is on. The LCD segment for COM9 is on. The LCD segments for COM1 to COM9 are on. Output pin state (S11) No. 6370 -19/39 LC75808E, 75808W 3. 1/10 duty Output Pin S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 COM1 D1 D11 D21 D31 D41 D51 D61 D71 D81 D91 D101 D111 D121 D131 D141 D151 D161 D171 D181 D191 D201 D211 D221 D231 D241 D251 D261 D271 D281 D291 D301 D311 D321 D331 D341 D351 D361 D371 D381 D391 D401 D411 D421 D431 D441 COM2 D2 D12 D22 D32 D42 D52 D62 D72 D82 D92 D102 D112 D122 D132 D142 D152 D162 D172 D182 D192 D202 D212 D222 D232 D242 D252 D262 D272 D282 D292 D302 D312 D322 D332 D342 D352 D362 D372 D382 D392 D402 D412 D422 D432 D442 COM3 D3 D13 D23 D33 D43 D53 D63 D73 D83 D93 D103 D113 D123 D133 D143 D153 D163 D173 D183 D193 D203 D213 D223 D233 D243 D253 D263 D273 D283 D293 D303 D313 D323 D333 D343 D353 D363 D373 D383 D393 D403 D413 D423 D433 D443 COM4 D4 D14 D24 D34 D44 D54 D64 D74 D84 D94 D104 D114 D124 D134 D144 D154 D164 D174 D184 D194 D204 D214 D224 D234 D244 D254 D264 D274 D284 D294 D304 D314 D324 D334 D344 D354 D364 D374 D384 D394 D404 D414 D424 D434 D444 COM5 D5 D15 D25 D35 D45 D55 D65 D75 D85 D95 D105 D115 D125 D135 D145 D155 D165 D175 D185 D195 D205 D215 D225 D235 D245 D255 D265 D275 D285 D295 D305 D315 D325 D335 D345 D355 D365 D375 D385 D395 D405 D415 D425 D435 D445 COM6 D6 D16 D26 D36 D46 D56 D66 D76 D86 D96 D106 D116 D126 D136 D146 D156 D166 D176 D186 D196 D206 D216 D226 D236 D246 D256 D266 D276 D286 D296 D306 D316 D326 D336 D346 D356 D366 D376 D386 D396 D406 D416 D426 D436 D446 COM7 D7 D17 D27 D37 D47 D57 D67 D77 D87 D97 D107 D117 D127 D137 D147 D157 D167 D177 D187 D197 D207 D217 D227 D237 D247 D257 D267 D277 D287 D297 D307 D317 D327 D337 D347 D357 D367 D377 D387 D397 D407 D417 D427 D437 D447 COM8 D8 D18 D28 D38 D48 D58 D68 D78 D88 D98 D108 D118 D128 D138 D148 D158 D168 D178 D188 D198 D208 D218 D228 D238 D248 D258 D268 D278 D288 D298 D308 D318 D328 D338 D348 D358 D368 D378 D388 D398 D408 D418 D428 D438 D448 COM9 D9 D19 D29 D39 D49 D59 D69 D79 D89 D99 D109 D119 D129 D139 D149 D159 D169 D179 D189 D199 D209 D219 D229 D239 D249 D259 D269 D279 D289 D299 D309 D319 D329 D339 D349 D359 D369 D379 D389 D399 D409 D419 D429 D439 D449 COM10 D10 D20 D30 D40 D50 D60 D70 D80 D90 D100 D110 D120 D130 D140 D150 D160 D170 D180 D190 D200 D210 D220 D230 D240 D250 D260 D270 D280 D290 D300 D310 D320 D330 D340 D350 D360 D370 D380 D390 D400 D410 D420 D430 D440 D450 Continued on next page. No. 6370 -20/39 LC75808E, 75808W Continued from preceding page. Output Pin S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 COM1 D451 D461 D471 D481 D491 D501 D511 D521 D531 D541 D551 D561 D571 D581 D591 COM2 D452 D462 D472 D482 D492 D502 D512 D522 D532 D542 D552 D562 D572 D582 D592 COM3 D453 D463 D473 D483 D493 D503 D513 D523 D533 D543 D553 D563 D573 D583 D593 COM4 D454 D464 D474 D484 D494 D504 D514 D524 D534 D544 D554 D564 D574 D584 D594 COM5 D455 D465 D475 D485 D495 D505 D515 D525 D535 D545 D555 D565 D575 D585 D595 COM6 D456 D466 D476 D486 D496 D506 D516 D526 D536 D546 D556 D566 D576 D586 D596 COM7 D457 D467 D477 D487 D497 D507 D517 D527 D537 D547 D557 D567 D577 D587 D597 COM8 D458 D468 D478 D488 D498 D508 D518 D528 D538 D548 D558 D568 D578 D588 D598 COM9 D459 D469 D479 D489 D499 D509 D519 D529 D539 D549 D559 D569 D579 D589 D599 COM10 D460 D470 D480 D490 D500 D510 D520 D530 D540 D550 D560 D570 D580 D590 D600 For example, the table below lists the segment output states for the S11 output pin. Display data D101 0 1 0 0 0 0 0 0 0 0 0 1 D102 0 0 1 0 0 0 0 0 0 0 0 1 D103 0 0 0 1 0 0 0 0 0 0 0 1 D104 0 0 0 0 1 0 0 0 0 0 0 1 D105 0 0 0 0 0 1 0 0 0 0 0 1 D106 0 0 0 0 0 0 1 0 0 0 0 1 D107 0 0 0 0 0 0 0 1 0 0 0 1 D108 0 0 0 0 0 0 0 0 1 0 0 1 D109 0 0 0 0 0 0 0 0 0 1 0 1 D110 0 0 0 0 0 0 0 0 0 0 1 1 The LCD segments for COM1 to COM10 are off. The LCD segment for COM1 is on. The LCD segment for COM2 is on. The LCD segment for COM3 is on. The LCD segment for COM4 is on. The LCD segment for COM5 is on. The LCD segment for COM6 is on. The LCD segment for COM7 is on. The LCD segment for COM8 is on. The LCD segment for COM9 is on. The LCD segment for COM10 is on. The LCD segments for COM1 to COM10 are on. Output pin state (S11) No. 6370 -21/39 LC75808E, 75808W Serial Data Output 1. When CL is stopped at the low level 2. When CL is stopped at the high level Note: B0 to B3, A0 to A3******CCB address `43H' KD1 to KD30 ............ Key data SA ............................ Sleep acknowledge data Note: If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge data(SA) will be invalid. Output Data 1. KD1 to KD30 : Key data When a key matrix of up to 30 keys is formed from the KS1 to KS6 output pins and the KI1 to KI5 input pins and one of those keys is pressed, the key output data corresponding to that key will be set to 1. The table shows the relationship between those pins and the key data bits. KI1 KS1 KS2 KS3 KS4 KS5 KS6 KD1 KD6 KD11 KD16 KD21 KD26 KI2 KD2 KD7 KD12 KD17 KD22 KD27 KI3 KD3 KD8 KD13 KD18 KD23 KD28 KI4 KD4 KD9 KD14 KD19 KD24 KD29 KI5 KD5 KD10 KD15 KD20 KD25 KD30 When the states of the KS1 to KS6 output pins during key scan standby are set to low for KS1 and KS2 and to high for KS3 to KS6 by the KC1 to KC6 bits in the control data and a key matrix of up to 20 keys is formed from the KS3 to KS6 output pins and the KI1 to KI5 input pins, the KD1 to KD10 key data bits will be set to 0. 2. SA : Sleep acknowledge data This output data bit is set to the state when the key was pressed. Also, while DO will be low in this case, if serial data is input and the mode is set (to normal or sleep mode) during this period, that mode will be set. SA will be 1 in sleep mode and 0 in normal mode. No. 6370 -22/39 LC75808E, 75808W Key Scan Operation Functions 1. Key scan timing The key scan period is 384T(s). To reliably determine the on/off state of the keys, the LC75808E/W scans the keys twice and determines that a key has been pressed when the key data agrees. It outputs a key data read request (a low level on DO) 800T(s) after starting a key scan. If the key data dose not agree and a key was pressed at that point, it scans the keys again. Thus the LC75808E/W cannot detect a key press shorter than 800T(s). *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 Note: *3. Note that the high/low states of these pins are determined by the KC1 to KC6 bits in the control data, and that key scan output signals are not output from pins that are set to low. 2. In normal mode * The pins KS1 to KS6 are set to high or low by the KC1 to KC6 bits in the control data. * If a key on one of the lines corresponding to a KS1 to KS6 pin which is set high is pressed, a key scan is started and the keys are scanned until all keys are released. Multiple key presses are recognized by determining whether multiple key data bits are set. 1 * If a key is pressed for longer than 800T(s) (Where T= ---- ) the LC75808E/W outputs a key data read request (a fosc low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if CE is high during a serial data transfer, DO will be set high. * After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75808E/W performs another key scan. Also note that DO, being an open-drain output, requires a pull-up resistor (between 1 k and 10 k). No. 6370 -23/39 LC75808E, 75808W 3. In sleep mode * The pins KS1 to KS6 are set to high or low by the KC1 to KC6 bits in the control data. * If a key on one of the lines corresponding to a KS1 to KS6 pin which is set high is pressed, the oscillator on the OSC pin is started and a key scan is performed. Keys are scanned until all keys are released. Multiple key presses are recognized by determining whether multiple key data bits are set. 1 * If a key is pressed for longer than 800T(s)(where T= ---- ) the LC75808E/W outputs a key data read request (a fosc low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if CE is high during a serial data transfer, DO will be set high. * After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75808E/W performs another key scan. However, this dose not clear sleep mode. Also note that DO, being an open-drain output, requires a pull-up resistor (between 1 k and 10 k). * Sleep mode key scan example Example: When the control data bits KC1 to KC5 are 0, KC6 is 1, and SP is 1. (sleep with only KS6 high) [L] [L] [L] [L] [L] [H] Note: *4.These diodes are required to reliable recognize multiple key presses on the KS6 line when sleep mode state with only KS6 high, as in the above example. That is, these diodes prevent incorrect operations due to sneak currents in the KS6 key scan output signal when keys on the KS1 to KS5 lines are pressed at the same time. Multiple Key Presses Although the LC75808E/W is capable of key scanning without inserting diodes for dual key presses, triple key presses on the KI1 to KI5 input pin lines, or multiple key presses on the KS1 to KS6 output pin lines, multiple presses other than these cases may result in keys that were not pressed recognized as having been pressed. Therefore, a diode must be inserted in series with each key. Applications that do not recognize multiple key presses of three or more keys should check the key data for three or more 1 bits and ignore such data. No. 6370 -24/39 LC75808E, 75808W 1/8 Duty, 1/4 Bias Drive Technique COM1 COM2 . . . . . . . . . . . . . . . . . COM8 LCD driver output when all LCD segments corresponding to COM1 to COM8 are turned off LCD driver output when only LCD segments corresponding to COM1 are turned on LCD driver output when only LCD segments corresponding to COM2 are turned on LCD driver output when all LCD segments corresponding to COM1 to COM8 are turned on No. 6370 -25/39 LC75808E, 75808W 1/9 Duty, 1/4 Bias Drive Technique COM1 COM2 . . . . . . . . . . . . . . . . . COM9 LCD driver output when all LCD segments corresponding to COM1 to COM9 are turned off LCD driver output when only LCD segments corresponding to COM1 are turned on LCD driver output when only LCD segments corresponding to COM2 are turned on LCD driver output when all LCD segments corresponding to COM1 to COM9 are turned on No. 6370 -26/39 LC75808E, 75808W 1/10 Duty, 1/4 Bias Drive Technique COM1 COM2 . . . . . . . . . . . . . . . . . COM10 LCD driver output when all LCD segments corresponding to COM1 to COM10 are turned off LCD driver output when only LCD segments corresponding to COM1 are turned on LCD driver output when only LCD segments corresponding to COM2 are turned on LCD driver output when all LCD segments corresponding to COM1 to COM10 are turned on No. 6370 -27/39 LC75808E, 75808W Voltage Detection Type Reset Circuit (VDET) This circuit generates an output signal and resets the system when logic block power is first applied and when the voltage drops, i.e., when the logic block power supply voltage is less than or equal to the power down detection voltage VDET, which is 3.0V, typical. To assure that this function operates reliably, a capacitor must be added to the logic block power supply line so that the logic block power supply voltage VDD rise time when the logic block power is first applied and the logic block power supply voltage VDD fall time when the voltage drops are both at least 1 ms. (See Figure 3, 4, and 5.) Power Supply Sequence The following sequences must be observed when power is turned on and off. (See Figure 3, 4, and 5.) * Power on :Logic block power supply(VDD) on LCD driver block power supply(VLCD) on * Power off:LCD driver block power supply(VLCD) off Logic block power supply(VDD) off However, if the logic and LCD driver blocks use a shared power supply, then the power supplies can be turned on and off at the same time. System Reset 1. Reset Function The LC75808E/W performs a system reset with the VDET. When a system reset is applied, the display is turned off, key scanning is disabled, the key data is reset, and the general-purpose output ports are set to and held at the low level (VSS). These states that are created as a result of the system reset can be cleared by executing the instruction described below. (See figure 3, 4, and 5.) * Clearing the display off state Transferring all the serial data (the display data and the control data) creates a state in which the display is turned on. * Clearing the key scan disabled and key data reset states Transferring the control data not only creates a state in which key scanning can be performed, but also clears the key data reset. * Clearing the general-purpose output ports locked at the low level (VSS) state Transferring the control data clears the general-purpose output ports locked at the low level (VSS) state and sets the states of the general-purpose output ports. * 1/8 duty VDD VLCD CE Internal data (KC1 to KC6, PC1 to PC4, CT0 to CT3, CTC, SC, SP, DT1, DT2) Internal data (D1 to D120) Internal data (D121 to D240) Undefined Undefined Defined Defined Undefined Undefined Undefined Undefined Defined Undefined Internal data (D241 to D360) Internal data (D361 to D480) Defined Defined Undefined Undefined Undefined Key scan General-purpose output ports Display state Disabled Fixed at the low level (VSS) Execution enabled Can be set to either the high (VDD) or low (VSS) level. Display off Display on * t1 1 ms (Logic block power supply voltage VDD rise time) * t2 0 * t3 0 * t4 1 ms (Logic block power supply voltage VDD fall time) Figure 3 No. 6370 -28/39 LC75808E, 75808W * 1/9 duty VDD VLCD CE Internal data (KC1 to KC6, PC1 to PC4, CT0 to CT3, CTC, SC, SP, DT1, DT2) Internal data (D1 to D135) Internal data (D136 to D270) Internal data (D271 to D405) Undefined Undefined Defined Defined Undefined Undefined Undefined Undefined Defined Undefined Defined Defined Execution enabled Undefined Undefined Internal data (D406 to D540) Key scan Undefined Disabled Fixed at the low level (VSS) General-purpose output ports Display state Can be set to either the high (VDD) or low (VSS) level. Display off Display on * t1 1 ms (Logic block power supply voltage VDD rise time) * t2 0 * t3 0 * t4 1 ms (Logic block power supply voltage VDD fall time) Figure 4 * 1/10 duty VDD VLCD CE Internal data (KC1 to KC6, PC1 to PC4, CT0 to CT3, CTC, SC, SP, DT1, DT2) Internal data (D1 to D150) Undefined Undefined Defined Defined Undefined Undefined Internal data (D151 to D300) Undefined Undefined Defined Undefined Internal data (D301 to D450) Internal data (D451 to D600) Defined Defined Undefined Undefined Undefined Key scan Disabled Fixed at the low level (VSS) Execution enabled General-purpose output ports Display state Can be set to either the high (VDD) or low (VSS) level. Display off Display on * t1 1 ms (Logic block power supply voltage VDD rise time) * t2 0 * t3 0 * t4 1 ms (Logic block power supply voltage VDD fall time) Figure 5 No. 6370 -29/39 LC75808E, 75808W 2. LC75808E/W internal block states during the system reset * CLOCK GENERATOR Reset is applied and the base clock is stopped. However, the OSC pin state (normal or sleep mode) is determined after the SP control data bit is transferred. * COMMON DRIVER, SEGMENT DRIVER & LATCH Reset is applied and the display is turned off. However, display data can be input to the latch circuit in this state. * CONTRAST ADJUSTER Reset is applied and operation of the display contrast adjustment circuit is disabled. After that, once CT0 to CT3 and CTC in the control data have been transferred to the IC it will then be possible to set the display contrast. * KEY SCAN, KEY BUFFER Reset is applied, these circuits are forcibly initialized internally, and key scan operation is disabled. Also, the key data is all set to 0. After that, once KC1 to KC6 in the control data have been transferred to the IC it will then be possible to perform key scan operations. * GENERAL PORT Reset is applied and the states of the general-purpose output ports are held fixed at the low level (VSS). * CCB INTERFACE, SHIFT REGISTER, CONTROL REGISTER Since serial data transfer is possible, these circuits are not reset. Blocks that are reset No. 6370 -30/39 LC75808E, 75808W 3. Output pin states during the system reset Output pin S1 to S60 COM1 to COM10 KS1 to KS6 P1 to P4 DO Note: *5. State during reset L (VLCD4) L (VLCD4) L (VSS) L (VSS) H *5 Since this output pin is an open-drain output, a pull-up resistor of between 1 k and 10 k is required. This pin is held at the high level even if a key data read operation is performed before the KC1 to KC6 control data has been transferred to the IC. Sample Application Circuit 1 1/8 duty, 1/4 bias drive technique (for use with normal panels) LCD panel +5 V *6 +8 V *7 C 0.047 F *8 From the controller To the controller To the controller power supply *9 general-purpose output ports Used with the backlight controller or other circuit. Key matrix (up to 30 keys) Note: *6. *7. *8. *9. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75808E/W is reset by the VDET. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to ground. If the function of the INH pin is not used, the INH pin must be connected to the logic block power supply VDD. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 k to 10 k) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. No. 6370 -31/39 LC75808E, 75808W Sample Application Circuit 2 1/8 duty, 1/4 bias drive technique (for use with large panels) LCD panel +5 V *6 +8 V *7 C 0.047 F 10 k R 2.2 k *8 From the controller To the controller To the controller power supply *9 general-purpose output ports Used with the backlight controller or other circuit. Key matrix (up to 30 keys) Note: *6. *7. *8. *9. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75808E/W is reset by the VDET. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to ground. If the function of the INH pin is not used, the INH pin must be connected to the logic block power supply VDD. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 k to 10 k) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. No. 6370 -32/39 LC75808E, 75808W Sample Application Circuit 3 1/9 duty, 1/4 bias drive technique (for use with normal panels) LCD panel +5 V *6 +8 V *7 C 0.047 F *8 From the controller To the controller To the controller power supply *9 general-purpose output ports Used with the backlight controller or other circuit. Key matrix (up to 30 keys) Note: *6. *7. *8. *9. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75808E/W is reset by the VDET. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to ground. If the function of the INH pin is not used, the INH pin must be connected to the logic block power supply VDD. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 k to 10 k) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. No. 6370 -33/39 LC75808E, 75808W Sample Application Circuit 4 1/9 duty, 1/4 bias drive technique (for use with large panels) LCD panel +5 V *6 +8 V *7 C 0.047 F 10 k R 2.2 k *8 From the controller To the controller To the controller power supply *9 general-purpose output ports Used with the backlight controller or other circuit. Key matrix (up to 30 keys) Note: *6. *7. *8. *9. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75808E/W is reset by the VDET. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to ground. If the function of the INH pin is not used, the INH pin must be connected to the logic block power supply VDD. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 k to 10 k) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. No. 6370 -34/39 LC75808E, 75808W Sample Application Circuit 5 1/10 duty, 1/4 bias drive technique (for use with normal panels) LCD panel +5 V *6 +8 V *7 C 0.047 F *8 From the controller To the controller To the controller power supply *9 general-purpose output ports Used with the backlight controller or other circuit. Key matrix (up to 30 keys) Note: *6. *7. *8. *9. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75808E/W is reset by the VDET. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to ground. If the function of the INH pin is not used, the INH pin must be connected to the logic block power supply VDD. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 k to 10 k) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. No. 6370 -35/39 LC75808E, 75808W Sample Application Circuit 6 1/10 duty, 1/4 bias drive technique (for use with large panels) LCD panel +5 V *6 +8 V *7 C 0.047 F 10 k R 2.2 k *8 From the controller To the controller To the controller power supply *9 general-purpose output ports Used with the backlight controller or other circuit. Key matrix (up to 30 keys) Note: *6. *7. *8. *9. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75808E/W is reset by the VDET. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to ground. If the function of the INH pin is not used, the INH pin must be connected to the logic block power supply VDD. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 k to 10 k) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. Notes on Transferring Display Data from the Controller The display data is transferred to the LC75808E/W in four operations. All of the display data should be transferred within 30 ms to maintain the quality of the displayed image. No. 6370 -36/39 LC75808E, 75808W Notes on the Controller Key Data Read Techniques 1. Timer based key data acquisition * Flowchart CE = [ L ] DO = [ L ] * Timing chart t5: Key scan execution time when the key data agreed for two key scans. (800T(s)) t6: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (1600T(s)) t7: Key address (43H) transfer time 1 T = ------ t8: Key data read time fosc * Explanation In this technique, the controller uses a timer to determine key on/off states and read the key data. The controller must check the DO state when CE is low every t9 period without fail. If DO is low, the controller recognizes that a key has been pressed and executes the key data read operation. The period t9 in this technique must satisfy the following condition. t9 > t6 + t7 + t8 If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge data (SA) will be invalid. No. 6370 -37/39 LC75808E, 75808W 2. Interrupt based key data acquisition * Flowchart CE = [ L ] DO = [ L ] CE = [ L ] DO = [ H ] * Timing chart t5: Key scan execution time when the key data agreed for two key scans. (800T(S)) t6: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (1600T(S)) t7: Key address (43H) transfer time 1 T = ------ t8: Key data read time fosc No. 6370 -38/39 LC75808E, 75808W * Explanation In this technique, the controller uses interrupts to determine key on/off states and read the key data. The controller must check the DO state when CE is low. If DO is low, the controller recognizes that a key has been pressed and executes the key data read operation. After that the next key on/off determination is performed after the time t10 has elapsed by checking the DO state when CE is low and reading the key data. The period t10 in this technique must satisfy the following condition. t10 > t6 If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge data (SA) will be invalid. Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of March, 2000. Specifications and information herein are subject to change without notice. PS No. 6370 -39/39 |
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